1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly to a semiconductor memory device suitable for a layout method of bit cells of a dual-port (2-port) SRAM.
2. Description of the Related Art
Recently, static random access memory (SRAM) has been widely used in computer cache memories and portable electronic products, because any refresh operation is not required in the SRAM, and thus less power is consumed and an operation speed is faster as compared to dynamic random access memory (DRAM). Bit cells used in SRAMs are of two types, i.e., high-resistance cells and complementary metal oxide semiconductor (CMOS) cells. CMOS cells are configured by a pair of transmission transistors, a pair of driving transistors, and a pair of load transistors (for example, see JP-A 2000-31297 (KOKAI)).
In a system-on-chip used for image processing communication processing or the like, there is a demand for mounting a dual-port SRAM that can be accessed simultaneously from both A and B ports for the purpose of increasing the speed of the processing. This dual-port SRAM is realized by further adding a pair of transmission transistors to the bit cells of a single-port SRAM.
For example, JP-A 2005-25863 (KOKAI) discloses a method for serving both purposes of data maintenance stability and writing margins for a 2-port SRAM that includes a latch circuit that complementarily maintains potentials in storage nodes, access transistors each distributed between the storage nodes and bit lines, and turned on in response to activation of word lines, write access transistors and storage level driving transistors each arranged between the storage node and a ground potential, the write access transistors being turned on in response to activation of the word lines and the storage level driving transistors being turned on in response to sub bit lines, and write access transistors that are turned on in response to the activation of the word lines and storage level driving transistors that are turned on in response to the sub bit lines.
However, in bit cells of a conventional dual-port SRAM, a pair of load transistors are positioned adjacent to each other in the horizontal direction, and in this state, while transmission transistors for different ports are positioned adjacent to each other in the horizontal direction, two transmission transistors each are aligned on either side of the load transistor (four transmission transistors in total). Thus, besides the fact that the vertical-to-horizontal aspect of the bit cells becomes about 1:4, and the length of the word line wired in the horizontal direction becomes longer, the width also becomes thinner. As a result, the resistance of the word line rises. Consequently, rising inclination of a word-line potential becomes smoother and the maximum frequency at the time of incorporating bit cells in a macro manner is controlled by the rising inclination of the word-line potential, and thus there is a problem that the operation speed of the SRAM is reduced.
In the bit cells of a conventional dual-port SRAM, the transmission transistors for different ports are positioned adjacent to each other in the horizontal direction, and thus the bit lines for different ports are also positioned adjacently. As a result, there is also a problem that the parity of bit lines is lost, and a variation in a static noise margin of bit cells increases.
Although it is possible to simultaneously write and read in the conventional dual-port SRAMs, only two word lines are distributed in each bit cell, and thus there is also a problem that it is not possible to simultaneously write one set of data and read the data with two read ports.